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asahi kasei [AK2346A] ms1289-e-02 2012/06 - 1 - AK2346A two-way radio audio processor 1. features ? audio processing ? tx and rx amplifier ? pre/de-emphasis circuit ? compressor and expander with no external components ? scrambler and de-scrambler in frequency inversion type with 16 different carrier clocks ? limiter with level adjuster ? splatter filter for wide and narrow band ? digital controlled amplifier for microphone, modulator and demodulator sensitivity ? 1200/2400bit/s msk modem with frame detection ? wide range operation voltage: 2.6v to 5.5v, temperature: -40 to 85 c ? oscillator circuit for 14.7456mhz crystal ? serial control interface operation ? compact plastic packaging, 24-pin qfnj (4.0 x 4.0 x 0.75mm 0.5mm pitch) 2. description AK2346A includes audio filter, limiter, splatter fi lter, compandor, scrambler, msk modem, which is highly integrated two-way radio baseband functions for frs and lmr. audio high-pass filter shows a high attenuation in magnitude response characteristics less than 250hz that supports to eliminate a sub-audio tone clearly. tx limiter for deviation control has a limiting level adjuster controlled by a 4-bit signal level adjuster. splatter filter has the magnitude response for narrowband (fc=2.55khz) and wideband (3.0khz) to meet various regulatory agencies in the world wide. compandor is no adjustment type because it incl udes all parametric components inside the chip. scrambler circuit is composed of frequency invers ion circuit by double balanced mixer that has 16 different carrier clocks. msk modem for data communication can be chosen either 2400bit/s or 1200bit/s. 2400bit/s data rate provides a high speed data transmission and 1200bit/s supports a low ber (bit error rate) performance that is suitable for under weak electrical field condition application. there are four signal level adjusters for microphone, modulator and demodulator sensitivity by digital controlled amplifier (volume).
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 2 - 3. contents 1. feat ures 1 2. descr ipti on 1 3. cont ents 2 4. block diagram 3 5. circuit c onfigurat ion 4 6. pin/f unction 5 7. absolute ma ximum ratings 8 8. recommended operat ing cond itions 8 9. digital dc c haracteri stics 8 10. clock input c haracteri stics 9 11. system reset 9 12. power c onsumption 10 13. analog char acterist ics 11 14. level diagr am 16 15. serial interfac e configur ation 17 16. digital ac ti ming 27 17. msk modem descrip tion 30 18. recommended external application circuits 33 19. packa ging 36 20. important notice 37
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 3 - 4. block diagram osc xin xout extino + vss1 rxout tx/rx _hpf scrambler/ descrambler fc = 300hz com- pressor pre- emphasis vr4 vr3 rxlpf expan- der mod de- emphasis filtero vr2 splatter smf - + rxa1 vr1 (hpf) - + txa1 txin txino rxin rxino fc = 2.55khz / 3.0khz -18 to +4.5/1.5db -4 to +3.5/0.5db -9.6 to +3.0 / 0.2db -18,-4.5 to +4.5 /0.25db adder 2 smf extin1 - + txa2 agnd + + agndin a gnd mskclk msk demodulator mskdat a power on at mode 1,2,3,4 power on at mode 2,4 power on at mode 3,4 power on at mode 2,3,4 20 19 11 10 12 control re g ister dio sclk dir rstn 2 3 4 23 78 14 15 5 6 3 22 tc em txrx pcont hpfsw txsw 2,1,0 rxsw em tc msksw 1,0 filsw 1,0 17 16 limiter limsw a vdd + 9 vss2 18 msk bpf msk modulator 1 24 div dac extin2 adder 1 dvdd pcont 21 pcont txrx txrx
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 4 - 5. circuit configuration block description txa1 the operational amplifier for transmit audio gain adjustment and for the filter to eliminate aliasing noise by the scf(switched capacitor filter) in the following stage. please select an external resistor and capacitor to set the gain less than 30db and the cut-off frequency to about 10khz. vr1 (hpf) digitally controlled amplifier (volume) for transm it audio signal level which is adjustable in 1.5db steps over a ?18.0db to +4.5db range by setting vr13 to vr10 register. compressor the circuit to compress transmits audio signal level by 1/2 in db scale. standard cross-point is ?10dbx. tc register sets off/on to the circuit. pre-emphasis the circuit to emphasis the high-frequency component of transmit audio signal to improve s/n ratio of the modulation signal. tx/rxhpf the high-pass filter to eliminate the low-frequency component less than 250hz for transmit and receive audio signal. this circuit is turned on and off by hpfsw register. scrambler/ descrambler scramble/de-scramble circuit to inverse transmit and receive audio spectrum by 2.844 to 3.491khz carrier signal. em and pcont register can set scramble/de-sc ramble or emphasis ci rcuit. both circuits can not be used simultaneously. adder1/2 the circuit to add audio signal and external tone signal. txinsw,txsw2,1,0 registers are used to set this block. limiter an amplitude limiting circuit to suppress the frequency deviation of the modulation signal. the limitation level can be adjusted by internal dac. dac digitally controlled amplifier (volume) for the limitation level of the limiter circuit which is adjustable in 0.5db steps over a -17.6db to -2.1db range by setting limlv3 tolimlv0 register. vr2 digitally controlled amplifier (volume) for mod output level which is adjustable in 0.2db steps over a ?3.2db to +3.0db range by setting vr25 to vr20 register. vr25 is a ?6.4/0db coarse bit. splatter the circuit to eliminate the high frequency component higher than 3khz included in the limiter output signal or the msk modulator signal. the cut-off frequency can be selected by spl register. smf the smoothing filter to eliminate the high frequency and clock component caused in scf circuits. rxa1 the operational amplifier for receives audio gain adjustment and for the filter to eliminate aliasing noise by the scf in the following stage. please select an external resistor and capacitor to set the gain less than 20db and the cut-off frequency to about 40khz. vr3 digitally controlled amplifier (volume) for rece ive audio signal level which is adjustable in 0.5db steps over a ?4.0db to +3.5db range by setting vr33 to vr30 register. rxlpf the low-pass filter to eliminate the high frequency component higher than 3khz for receive audio signal. de-emphasis the circuit to de-emphasis the emphasized signal by pre-emphasis circuit. expander the circuit to expand the receive audio signal level to double in db scale compressed by compressor standard cross-point is ?10dbx. tc register sets off/on to the circuit. vr4 digitally controlled amplifier (volume) for expander output level which is adjustable in 0.25db, steps over a ?18db and ?4.5db to +4.5db range by setting vr42 to vr40 register. txa2 the operational amplifier for transmit audio gain adjustment and for the filter to eliminate aliasing noise by the scf(switched capacitor filter) in the following stage. please select an external resistor and capacitor to set the gain less than 30db and the cut-off frequency to about 10khz.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 5 - block description msk bpf the band-pass filter to eliminate the low and high frequency component for received msk signal. msk demodulator the circuit to reproduce the 1200/2400bit/s receive clock and data from msk signal at rxin pin. msk modulator the circuit to generate a msk signal according to the received digital data from mskdata pin. agnd the circuit to generate the reference voltage (1/2vdd) for internal analog signal. osc the circuit to oscillate the 14.7456mhz reference clock with an external crystal oscillator and resistor and capacitors. div the circuit to generate 1/2,1/3 or 1/4 freque ncy-divided output when a signal whose frequency is twice, three times, or four times higher than 3.6864mhz is input from the outside, this circuit divides the signal frequency by two, three, or four. mcksl[1:0] register is used to set this block. control register the control register controls the status of internal switches and digitally controlled amplifiers of ic by serial data that consists of 4 address bits and 8 data bits. the data buffer stores 8 bits of the msk receiv ed data to smooth the signal interface with microprocessor. at the start up, rstn-pin is used for syst em reset. srst register is used for software reset. (refer to the control register map) 6. pin/function package signal pin no name type conditions at power down function 1 mskclk do h clock input and output pin for msk signal. 2 dio db z serial data input and output pin. input for register setting data and output for msk receive data. 3 sclk di z clock input pin for serial data i/o. 4 dir di z serial data i/o control pin. 5 xout do *2) crystal oscillator connecting input pin. 6 xin di *2) crystal oscillator connecting input and output pin. to connect a 14.7456mhz crystal oscillator between this pin and xout pin generates the reference clock internally. in case of externally supplied clock operation, connect to this pin. for more information, please refer to external application circuits. 7 dvdd pwr - digital vdd power supply pin. normally connect to 2.6v to 5.5v power-supply. also this pin must be decoupled to vss pin by 0.1uf capacitor mounted close to the device pins. 8 vss1 pwr - vss power supply pin. normally supply 0v to this pin. 9 avdd pwr - analog vdd power supply pin. normally connect to 2.6v to 5.5v power-supply. also this pin must be decoupled to vss pin by 0.1uf capacitor mounted close to the device pins. applied voltage must be dvdd avdd
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 6 - package signal pin no name type conditions at power down function 10 rxin ai z demodulated audio signal input pin. this is the inverting input of rxa1. it composes a pre-filter with external resistor and capacitor. 11 rxino ao z rxa1 feedback output pin. 12 filtero ao z rxlpf circuit and tx/rx_hpf circuit output pin. lpf output pin. this is a monitor pin for tone signal. 57.6khz sampling-clock is included, so please eliminate this signal component by lpf externally. 13 rxout ao z receive audio signal output pin. 14 agndin ai *1) analog ground input pin. connect the capacitor to stabilize the analog ground level. 15 agnd ao *1) analog ground output pin. connect the capacitor to stabilize the analog ground level. 16 extin1 ai z txa2 feedback input pin. this is the inverting input pin for txa2. it composes a microphone amplifier with an external resistor and capacitor. 17 extino ao z txa2 feedback output pin. 18 vss2 pwr - vss power supply pin. normally supply 0v to this pin. 19 txin ai z transmit audio signal input pin. this is the inverting input pin for txa1. it composes a microphone amplifier with an external resistor and capacitor. 20 txino ao z txa1 feedback output pin. 21 extin2 ai z external input pin. this pin is available for external tone signal. 22 mod ao z the modulated transmit signal output pin. 23 rstn di z reset pin. 24 mskdata db z msk signal msk signal transmitted and received data input and output pin. in transmission, AK2346A reads data synchronized with the rising edge of mskclk. this pin outputs 2 kinds of information according to the setting of fsl register . this pin puts out two types of signal that depends on the status of register named fsl. in case fsl equal ?1?, it is rece ived flag mode (rdf). so the pin puts out low level after 8 bits of msk receive signal have been written to the in ternal register. in case fsl equal ?0?, it is frame detection mode (fd). so the low pulse is put out after a frame pattern is detected. when msksw[1:0] register is set to ?1/0?, rdata signal is put out. note a : analog, d : digital, pwr : power, i : input, o : output, b : bidirectional , z : high-z, l : low *1) agnd level *2) when xin pin is set to low level, xout pin goes to high level.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 7 - ? pin assignment sclk dio txin txino xi n a gndin 3 2 19 20 6 14 extin2 dvdd 7 xout 5 di r 4 extino 17 mskcl k 1 vss1 8 a vdd 9 vss2 18 rxin 10 rxout 13 filtero 12 rxino 11 extin1 16 a gnd 15 mod 22 rstn 23 mskdata 24 21
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 8 - 7. absolute maximum ratings parameter symbol min. max. units avdd -0.3 6.5 v power supply voltage dvdd -0.3 6.5 v ground level vss 0 0 v -0.3 avdd+0.3 v input voltage v in -0.3 dvdd+0.3 v input current (except power supply pin) i in -10 +10 ma storage temperature t stg -55 130 c note : all voltages with respect to the vss pin. caution : exceeding these maximum ratings can result in damage to the device. normal operation cannot be guaranteed under this extreme. 8. recommended operating conditions parameter symbol condition min. typ. max. units operating temperature ta -40 85 c avdd 2.6 3.0 5.5 v power supply voltage dvdd dvdd avdd 2.6 3.0 5.5 v analog reference voltage agnd 1/2avdd v r l1 mod, rxout, filteroo 10 output load resistance r l2 txino, rxino, rxout 30 k c l1 mod, rxout, filteroo 50 output load capacitance c l2 txino, rxino, rxout 15 pf note : all voltages with respect to the vss pin. 9. digital dc characteristics parameter symbol condition min. typ. max. units high level input voltage v ih dio,sclk,dir,mskdata, rstn 0.8vdd v low level input voltage v il dio,sclk,dir,mskdata, rstn 0.2vdd v high level input current i ih v ih =dvdd dio,sclk,dir,mskdata, rstn 10 a low level input current i il v il =0v dio,sclk,dir,mskdata, rstn -10 a high level output voltage v oh i oh =+0.2ma mskclk,mskdata,dio vdd-0.4 vdd v low level output voltage v ol i ol =-0.4ma mskclk,mskdata,dio 0.0 0.4 v
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 9 - 10. clock input characteristics parameter symbol condition min. typ. max. unit remarks mck0 xin,xout 14.7456 mhz clock frequency mck1 xin 3.6864 7.3728 11.0592 14.7456 mhz *1), *2) high level input voltage v mck1_ih xin 1.5 v *1) low level input voltage v mck1_il xin 0.4 v *1) input amplitude v mck2 xin 0.2 1.0 v pp *2) *1) these values apply when the clock signal is input on the xin pin directly. for details, refer to 6), "oscillator circuit", in "recommended external circuit examples". *2) these values apply when the clock signal is input on the xin pin via dc cut. for details, refer to 6), "oscillator circuit", in "rec ommended external circuit examples". 11. system reset parameter symbol condition min. typ. max. unit remarks hardware reset signal input width t rstn rstn pin 1 s *1) software reset srst register *2) *1) after power-on, be sure to perform a hardware reset operation (register initialization). the system is reset by a low pulse input of 1 s (min.) and enters the normal operation state. at this moment, the digital (di) pins are set as follows: rstn pin to high, mskdata pin to low, sclk pin to high, dir pin to low. *2) when data 0xaa:10101010 is written to the srst[7:0] register, software reset is performed. this setting initializes the registers and the operation mode is set to mode 0 (power down). after software reset is completed, this register comes to ?0?. rstn v ih v il t rstn
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 10 - 12. power consumption parameter symbol condition min. typ. max. units idd0 mode 0 osc:off, audio: off, modem:off 0.1 0.3 idd1 mode 1 osc:on , audio: off, modem:off 0.8 1.5 idd2 mode 2 osc:on , audio: on , modem:off 5.4 8.7 idd3 mode 3 osc:on , audio: off, modem:on 1.8 3.2 consumption current idd4 mode 4 osc:on , audio: on , modem:on 6.0 9.5 ma
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 11 - 13. analog characteristics for the following conditions unless otherwise s pecified: f=1khz, emphasis: on, compandor: on, scrambler: off, vr1=vr2=vr3=vr4=0db with the external circuit shown in example page.33 to 35. ?dbx? is standardized unit for 2.6v to 5.5v oper ation, 0dbx=-5+20log(vdd/2)dbm, 0dbm=0.775vrms. 1) tx audio system parameter condition min. typ. max. units notes standard input level @txino -10 dbx absolute gain txino to mod -1.5 0 +1.5 db limit level extlimin to mod -8.6 -7.6 -6.6 dbx compressor linearity txino to mod txino=-44dbx txino=-50dbx relative value to 0db for mod level of -10dbx txino. -20.0 -24.0 -17.0 -20.0 -14.0 -16.0 db compressor distortion txino to mod txino=-10dbx 30khz low-pass filtering -35 db noise level with no signal input txino to mod c-message filtering -36.5 dbm vr1 attenuation error txino to mod -18.0 db to 4.5db, 1.5db/step -1.5 +1.5 db vr2 att error (vr24,23,22,21,20) txino to mod -3.2db to +3.0db, 0.2db/step -0.2 +0.2 db vr2 att error (vr25=0) txino to mod when -6.4db setting relative error for -6.4/0db -6.8 -6.4 -6.0 db limiter dac error (vr25=0) mod -10 +5.5db, 0.5db/step -0.5 +0.5 db 2) rx audio system parameter condition min. typ. max. units notes standard input level @rxino -10 dbx rxino to filtero -1.5 0 +1.5 db absolute gain rxino to rxout -1.5 0 +1.5 db expander linearity rxino to rxout rxino=-25dbx rxino=-30dbx relative value to 0db for rxout level of -10dbx rxino -33.0 -45.0 -30.0 -40.0 -27.0 -35.0 db expander distortion rxino to rxout rxino=-5dbx 30khz low-pass filtering -35 db noise level with no signal input rxino to rxout c-message filtering -70 dbm vr3 attenuation error rxin0 to rxout -4.0db to +3.5db, 0.5db/step -0.5 +0.5 db vr4 attenuation error rxin0 to rxout -4.5 to +4.5db, 0.25db/step -0.25 +0.25 db vr4 att error (vr42,41,40=0,0,0) rxin0 to rxout when -18db setting relative error for -18/0db -20 -18 -16 db
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 12 - 3) audio filter characteristics 3.1) emphasis: off , compandor: off, scrambler: off (design target values) parameter condition min. typ. max. units notes 250hz -50 -38 db 300hz to 2.0khz 2.5khz 3.0khz 6.0khz -1.0 -1.5 -4.0 -38 +1.0 +1.0 -1.0 -28 db spl =0 fc=2.55k tx overall characteristics txino to mod relative value to gain at 1khz 300hz to 2.5khz 3.0khz 6.0khz -1.0 -1.5 -43 +1.0 +1.0 -22 db spl =1 fc=3.0k rx overall characteristics rxino to rxout relative value to gain at 1khz 250hz 300hz 350hz to 3.0khz 6.0khz -1.5 -1.0 -49 -38 -38 +1.0 +1.0 -28 db 3.2) emphasis: on , compandor: off, scrambler: off parameter condition min. typ. max. units notes 250hz -57 -40 db 300hz 2.5khz 3.0khz 6.0khz -12.5 +6.0 +4.5 -29 -9.5 +9.0 +8.5 -18 db spl =0 fc=2.55k tx overall characteristics txino to mod relative value to gain at 1khz 300hz 2.5khz 3.0khz 6.0khz -12.5 +6.0 +7.0 -34 -9.5 +9.0 +10.5 -12 db spl =1 fc=3.0k rx overall characteristics rxino to rxout relative value to gain at 1khz 250hz 300hz 3.0khz 6.0khz +8.5 -11.5 -38 -52 -26 +11.5 -8.5 -40 db
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 13 - ? audio path frequency response (emphasis:off) figure 1: tx overall re sponse without pre-emphasis. figure 2: rx overall re sponse without de-emphasis. -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db) spl=0 spl=1 -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db)
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 14 - ? audio path frequency response (emphasis:on) figure 3: tx overall response with pre-emphasis. figure 4: rx overall response with de-emphasis. -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db) spl=0 spl=1 -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db)
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 15 - 4) scrambler characteristics (scrambler: on , emphasis: off, compandor: off) parameter condition min. typ. max. units notes carrier frequency 3.388 khz modulated output level txino to mod, rxino to rxout input level 1.0khz -10dbx measuring-freq. 2.388khz -12 -10 -8 dbx high frequency rejection level txino to mod, rxino to rxout input level 1.0khz -10dbx measuring-freq. 4.388khz -50 dbx carrier signal leakage level txino to mod, rxino to rxout input level no signal measuring-freq. 3.388khz -50 dbx original signal leakage level txino to mod, rxino to rxout input level 1.0khz -10dbx measuring-freq. 1.0khz -50 dbx 5) msk modem characteristics parameter condition min. typ. max. units notes tx signal level @mod 1.2khz signal out -12 -11 -10 dbx tx signal distortion @mod 1.2khz signal out -32 db rx signal level @rxino 1.2khz signal out -17 -11 -1 dbx
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 16 - 14. level diagram 1) tx audio system : txrx =0 2) rx audio system : txrx =1 ?dbx? is standardized unit for 2.6v to 5.5v oper ation, 0dbx=-5+20log(vdd/2)dbm, 0dbm=0.775vrms. smf limitter sp l a t t er +vr2 txa1 vr1 compres sor pre-emphasi s txhpf msk modulator scrm /descrm 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 txino +4. 5 -1 8 db 0 +3. 0 -9.2 db 0 crosspoint -10dbx 0db 0db -7.6dbx extin2 0 -10 -44 -50 -3 0 -2 7 -1 8 -5.5 - 5 -10 -11 -7.0 -19.2 -11dbx (msk) -10dbx (audio) dbx txi n mod g = 30db -27dbx -30dbx 0db 0d b f=1khz smf expander rxa1 vr3 rxlpf de-emphasi s rxhpf scrm /descrm 10 0 -10 -20 -25 -30 -40 -45 -50 -60 rxino +3.5 -4.0 db 0 +4.5 -18.0 db 0 cro sspoi nt -10dbx -5 db -5 db +5db -5 -10 -25 -30 -25 -20 -14 -6 . 5 - 5 0 -10 -5.5 -28 0 dbx (max.) -10dbx (typ.) dbx r xi n rxout vr 4 g = 20db 0db g = 0 d b -40dbx -50db x -5 0 -4 0 f=1kh z filter o
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 17 - 15. serial interface configuration 1) register configuration address data a3 a2 a1 a0 function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 control register 1 bs3 bs2 bs1 txrx txinsw txsw2 txsw1 txsw0 0 0 0 1 control register 2 filsw1 filsw0 rxsw limsw tc em pcont spl 0 0 1 0 control register 3 0 txa2pw msksw1 msksw0 msksl fcln fsl hpfsw 0 0 1 1 volume register 1 0 0 0 0 vr13 vr12 vr11 vr10 0 1 0 0 volume register 2 0 0 vr25 vr24 vr23 vr22 vr21 vr20 0 1 0 1 volume register 3 0 0 0 0 vr33 vr32 vr31 vr30 0 1 1 0 volume register 4 0 0 vr45 vr44 vr43 vr42 vr41 vr40 0 1 1 1 modem register 1 lower 8 bit of modem flame pattern 1 0 0 0 modem register 2 upper 8 bit of modem flame pattern 1 0 0 1 volume register 5 0 0 0 limlv4 limlv3 limlv2 limlv1 limlv0 1 0 1 0 control register 4 0 0 0 0 scr3 scr2 scr1 scr0 1 0 1 1 control register 5 0 0 0 0 0 mckcnt mcksl1 mcksl0 1 1 0 0 software reset srst[7:0] 1 1 0 1 test register 1 test register 1 for lsi test operation (not accessible) 1 1 1 0 test register 2 test register 2 for lsi test operation (not accessible) 1 1 1 1 test register 3 test register 3 for lsi test operation (not accessible) modem register 3 modem receive data
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 18 - 2) register map 2.1) control register 1 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 bs3 bs2 bs1 txrx txinsw txsw2 txsw1 txsw0 initial value 0 0 0 1 1 1 1 1 2.1.1) operation mode setting bs3 bs2 bs1 mode osc,agnd tx, rx, audio modem 0 0 0 mode0(power off) off off off 0 0 1 mode1(standby) on off off 0 1 0 mode2 on on off 0 1 1 mode3 on off on 1 0 0 mode4 on on on note : do no set the combination of the code which is not defined in the table given above. 2.1.2) tx, rx setting operation data function 0 1 notes txrx tx, rx switch tx operation note 1 rx operation note 2 note 3 txinsw tx signal txa1+txa2 operation txa1 operation note 4 2.1.3) tx audio path setting txsw2 txsw1 txsw0 tx audio modem extino signal extin2 signal 1 1 1 off off off off 1 1 0 on off off off 1 0 1 off on off off 1 0 0 on off on off 0 1 1 on off off on 0 1 0 off off on off 0 0 1 off off off on note : do no set the combination of the code which is not defined in the table given above. note 1: txin to rxout path is available by setting txrx=0 and rxsw=1 in register. however, scrambler/descrambler circuit does not work properly on this setting, so please set pcont=1 (disable). to set rxsw=0 makes rxout pin mute in operation. note 2: rxin to mod path is available by setting txrx=1 and txsw2/txsw1/txsw0=1/1/0 in register. however, scrambler/descrambler circuit does not work properly on this setting, so please set pcont=1 (disable). to set txsw2/txsw1/txsw 0=1/1/1 makes mod pin mute in operation. note 3: please set a gain level properly in each ci rcuit block according to level diagram in page 16. note 4: in case of txa1 +txa2 operation (txinsw=0), please set the register to other than txsw2/txsw1/txsw0=1/0/0 nor txsw2/txsw1/txsw0=0/1/0
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 19 - 2.2) control register 2 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 filsw1 filsw0 rxsw limsw tc em pcont spl initial value 1 1 1 1 1 1 1 1 filsw1 filsw0 operation notes 1 1 filtero pin is mute 0 1 rxlpf circuit signal to filtero pin 0 0 tx/rx_hpf circuit signal to filtero pin note : do no set the combination of the code which is not defined in the table given above. operation data function 0 1 notes rxsw rx audio mute normal operation note 5 limsw limiter off (bypass) on (active) tc compressor/ expander off (bypass) on (active) spl splatter cut-off frequency 2.55khz 3.0khz note 5: filtero pin cannot be controlled by setting rxsw=0. em pcont operation notes 1 1 emphasis : on (enable) scrambler : off(disable) 0 1 emphasis : off(disable) scrambler : off(disable) 0 0 emphasis : off(disable) scrambler : on (enable) note : do no set the combination of the code which is not defined in the table given above. 2.3) control register 3 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 txa2pw msksw1 msksw0 msksl fcln fsl hpfsw initial value 0 0 1 1 1 1 1 1 operation msksw1 msksw0 mskclk pin mskdata pin notes 1 1 high output high-z input high or low msk transmission :off 0 1 tx clock (tclk) is out put from mskclk pin. tx data (mskdata) can be input from mskdata pin. msk transmission :on 1 0 rx clock (rclk) is out put from mskclk pin. rx data (rdata) is output from mskdata pin. 0 0 high output rdf/fd signal is output from mskdata pin. select msk rx flag (rdf) and input clock to sclk pin, then rx data is output from dio pin.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 20 - operation data function 0 1 notes txa2pw txa2 power down control txa2 power down txa2 operation however in case of mode0, txa2 comes to power down. msksl modem data rate 2400bit/s 1200bit/s fcln modem flame detect on (enable) off (disable) fsl rdf/fd switch fd enable rdf enable hpfsw tx/rx_hpf off (bypass) on (active) 2.4) volume register 1 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 0 0 0 0 vr13 vr12 vr11 vr10 initial value 0 0 0 0 1 1 0 0 vr13 vr12 vr11 vr10 vr1 gain(db) 0 0 0 0 -18.0 0 0 0 1 -16.5 0 0 1 0 -15.0 0 0 1 1 -13.5 0 1 0 0 -12.0 0 1 0 1 -10.5 0 1 1 0 -9.0 0 1 1 1 -7.5 1 0 0 0 -6.0 1 0 0 1 -4.5 1 0 1 0 -3.0 1 0 1 1 -1.5 1 1 0 0 0.0 1 1 0 1 +1.5 1 1 1 0 +3.0 1 1 1 1 +4.5
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 21 - 2.5) volume register 2 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 0 0 vr25 vr24 vr23 vr22 vr21 vr20 initial value 0 0 1 1 0 0 0 0 vr25 vr2 gain(db) 0 -6.4 1 0.0 vr24 vr23 vr22 vr21 vr20 vr2 gain(db) 0 0 0 0 0 -3.2 0 0 0 0 1 -3.0 0 0 0 1 0 -2.8 0 0 0 1 1 -2.6 0 0 1 0 0 -2.4 0 0 1 0 1 -2.2 0 0 1 1 0 -2.0 0 0 1 1 1 -1.8 0 1 0 0 0 -1.6 0 1 0 0 1 -1.4 0 1 0 1 0 -1.2 0 1 0 1 1 -1.0 0 1 1 0 0 -0.8 0 1 1 0 1 -0.6 0 1 1 1 0 -0.4 0 1 1 1 1 -0.2 1 0 0 0 0 0.0 1 0 0 0 1 +0.2 1 0 0 1 0 +0.4 1 0 0 1 1 +0.6 1 0 1 0 0 +0.8 1 0 1 0 1 +1.0 1 0 1 1 0 +1.2 1 0 1 1 1 +1.4 1 1 0 0 0 +1.6 1 1 0 0 1 +1.8 1 1 0 1 0 +2.0 1 1 0 1 1 +2.2 1 1 1 0 0 +2.4 1 1 1 0 1 +2.6 1 1 1 1 0 +2.8 1 1 1 1 1 +3.0
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 22 - 2.6) volume register 3 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 0 vr33 vr32 vr31 vr30 initial value 0 0 0 0 1 0 0 0 vr33 vr32 vr31 vr30 vr3 gain (db) 0 0 0 0 -4.0 0 0 0 1 -3.5 0 0 1 0 -3.0 0 0 1 1 -2.5 0 1 0 0 -2.0 0 1 0 1 -1.5 0 1 1 0 -1.0 0 1 1 1 -0.5 1 0 0 0 0.0 1 0 0 1 +0.5 1 0 1 0 +1.0 1 0 1 1 +1.5 1 1 0 0 +2.0 1 1 0 1 +2.5 1 1 1 0 +3.0 1 1 1 1 +3.5
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 23 - 2.7) volume register 4 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 vr45 vr44 vr43 vr42 vr41 vr40 initial value 0 0 0 1 0 0 1 1 vr45 vr44 vr43 vr42 vr41 vr40 vr4 gain (db) 0 0 0 0 0 0 -18.0 0 0 0 0 0 1 -4.50 0 0 0 0 1 0 -4.25 0 0 0 0 1 1 -4.00 0 0 0 1 0 0 -3.75 0 0 0 1 0 1 -3.50 0 0 0 1 1 0 -3.25 0 0 0 1 1 1 -3.00 0 0 1 0 0 0 -2.75 0 0 1 0 0 1 -2.50 0 0 1 0 1 0 -2.25 0 0 1 0 1 1 -2.00 0 0 1 1 0 0 -1.75 0 0 1 1 0 1 -1.50 0 0 1 1 1 0 -1.25 0 0 1 1 1 1 -1.00 0 1 0 0 0 0 -0.75 0 1 0 0 0 1 -0.50 0 1 0 0 1 0 -0.25 0 1 0 0 1 1 0.00 0 1 0 1 0 0 +0.25 0 1 0 1 0 1 +0.50 0 1 0 1 1 0 +0.75 0 1 0 1 1 1 +1.00 0 1 1 0 0 0 +1.25 0 1 1 0 0 1 +1.50 0 1 1 0 1 0 +1.75 0 1 1 0 1 1 +2.00 0 1 1 1 0 0 +2.25 0 1 1 1 0 1 +2.50 0 1 1 1 1 0 +2.75 0 1 1 1 1 1 +3.00 1 0 0 0 0 0 +3.25 1 0 0 0 0 1 +3.50 1 0 0 0 1 0 +3.75 1 0 0 0 1 1 +4.00 1 0 0 1 0 0 +4.25 1 0 0 1 0 1 +4.50 note : do no set the combination of the code which is not defined in the table given above.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 24 - 2.8) modem register address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 f07 f06 f05 f04 f03 f02 f01 f00 initial value 1 0 1 0 1 0 0 0 1 0 0 0 f15 f14 f13 f12 f11 f10 f09 f08 initial value 0 0 0 1 1 0 1 1 2.9) volume register 5 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 0 0 limlv4 limlv3 limlv2 limlv1 limlv0 initial value 0 0 0 0 1 0 1 1 limlv4 limlv3 limlv2 limlv1 limlv0 gain(db) 0 0 0 0 0 5.5 (-2.1) 0 0 0 0 1 5.0 (-2.6) 0 0 0 1 0 4.5 (-3.1) 0 0 0 1 1 4.0 (-3.6) 0 0 1 0 0 3.5 (-4.1) 0 0 1 0 1 3.0 (-4.6) 0 0 1 1 0 2.5 (-5.1) 0 0 1 1 1 2.0 (-5.6) 0 1 0 0 0 1.5 (-6.1) 0 1 0 0 1 1.0 (-6.6) 0 1 0 1 0 0.5 (-7.1) 0 1 0 1 1 0 (-7.6dbx) 0 1 1 0 0 -0.5 (-8.1) 0 1 1 0 1 -1.0 (-8.6) 0 1 1 1 0 -1.5 (-9.1) 0 1 1 1 1 -2.0 (-9.6) 1 0 0 0 0 -2.5 (-10.1) 1 0 0 0 1 -3.0 (-10.6) 1 0 0 1 0 -3.5 (-11.1) 1 0 0 1 1 -4.0 (-11.6) 1 0 1 0 0 -4.5 (-12.1) 1 0 1 0 1 -5.0 (-12.6) 1 0 1 1 0 -5.5 (-13.1) 1 0 1 1 1 -6.0 (-13.6) 1 1 0 0 0 -6.5 (-14.1) 1 1 0 0 1 -7.0 (-14.6) 1 1 0 1 0 -7.5 (-15.1) 1 1 0 1 1 -8.0 (-15.6) 1 1 1 0 0 -8.5 (-16.1) 1 1 1 0 1 -9.0 (-16.6) 1 1 1 1 0 -9.5 (-17.1) 1 1 1 1 1 -10.0 (-17.6)
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 25 - 2.10) control register 4 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 0 0 0 scr3 scr2 scr1 scr0 initial value 0 0 0 0 1 1 0 1 scr3 scr2 scr1 scr0 carrier frequency (khz) 0 0 0 0 2.844 0 0 0 1 2.880 0 0 1 0 2.916 0 0 1 1 2.954 0 1 0 0 2.992 0 1 0 1 3.032 0 1 1 0 3.072 0 1 1 1 3.114 1 0 0 0 3.156 1 0 0 1 3.200 1 0 1 0 3.245 1 0 1 1 3.291 1 1 0 0 3.339 1 1 0 1 3.388 1 1 1 0 3.439 1 1 1 1 3.491 2.11) control register 5 address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 1 0 0 0 0 0 mckcnt mcksl1 mcksl0 initial value 0 0 0 0 0 1 1 1 operation data function 0 1 notes mckcnt external input switch external input a crystal oscillator (14.7456mhz) mcksl1 mcksl0 operation notes 0 0 master clock: 3.6864mhz external input only 1 0 master clock: 7.3728mhz external input only 0 1 master clock: 11.0592mhz external input only 1 1 master clock: 14.7456mhz note : set msksl[1:0] register when mode0 or mode1.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 26 - 2.12) software reset register address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 srst[7:0] initial value 0 0 0 0 0 0 0 0 when data 0xaa:10101010 is written to the srst[7:0] register, software reset is performed. refer to system reset for further information. 2.13) modem receive data register address data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 msk receive data data function 0 1 notes msksl=0 2.4khz 1.2khz rd7 to 0 msksl=1 1.8khz 1.2khz data received first is rd7.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 27 - 16. digital ac timing 1) serial interface timing parameter symbol min. typ. max. units clock pulse width 1 clock pulse width 2 ta tb 500 500 ns dio set up time dio hold time tc td 100 100 ns dir set up time dir hold time dir falling to sclk falling time te tf tg 100 100 100 ns sclk input rising time sclk input falling time th ti 100 100 ns sclk di/o dir a 3 a 2 a 1 d 1 d 0 tf tg te tb ta 0.8vdd 0.2vdd ti th sclk wavef orm a 0 tc td
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 28 - 2) msk modulator timing parameter symbol min. typ. max. units msksw1 falling to mskclk rising msksl=?0? msksl=?1? t1 208.3 416.7 us mskclk period msksl=?0? msksl=?1? t2 416.7 833.3 us mskdata set up time mskdata hold time mskdata hold time2 ts th th2 1 1 2 us note: the timing of setting the internal registers txsw1 and txsw2 is synchronized with the falling edge of dir pin. 3) msk demodulator timing parameter symbol min. typ. max. units rclk period and fd pulse width msksl=?0? msksl=?1? t 416.7 833.3 us rdf falling to sclk falling time sclk rising to rdf falling time tj tk 100 600 ns mskclk msksw0 mskdata th ts t1 t2 msksw1 (msksl=?0?) ( msksl=?1? ) register data th2 mod
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 29 - rxin rclk rdata fcln rdf/fd rdf/fd sclk di/o dir md 6 md 5 md 4 md 3 md 2 md 1 md 0 md 7 msksl=?0? msksl=?1? t t (internal node) (register data) a b c d (internal node) rxin rclk rdata fcln rdf/fd rdf/fd scl k di/o di r md 6 md 5 md 4 md 3 md 2 md 1 md 0 md 7 md 7 md 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 a 2 a 1 a 0 d7 tk t j d1 d 0 d e f g
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 30 - 17. msk modem description 1) msk modulator control flow msk data transmitter, modulator interfaces wi th mskclk, mskdata and mod pins and also txrx, txsw2, txsw1, txsw0 , msksw1 and msksw0 register as below. (1) setting txrx=0, msksw1=0, msksw0=1, txsw2=1 and txsw1=0, msk data transmit is provided. (2) a 1200/2400hz clock is put out from mskclk pin. synchronizing with the rising edge of mskclk, AK2346A reads the msk transmit data from mskdata pin and puts out them to mod pin. (3) after transmitting the necessary bit number, please set msksw1=1 (4) afterwards, before switching to audio signal mode, please wait for at least 2ms after setting msksw1=1 to complete sending the msk data final data bit transmit. then set txsw[2:0]=?1/1/0?. : msk data transmit compete : switching to audio signal txrx=0 msksw[1:0]=0/1 txsw[2:0]=1/0/1 y n msksw1=1 waiting 2ms or more msksw1=0 required bit number completed : msk data transmit start : msk data transmitting y msk data are transmitted synchronized to mskclk clock
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 31 - 2) msk demodulator control flow 2.1) when frame detection is used msk data receiver, demodulator interfaces with rxin, mskdata, sclk, dio and dir pins and also fsl, rxsw and fcln registers as below. (1) set msksw1=0 and msksw0=0 for flame detect mode. (2) setting fcln=0 and fsl=0 and also sclk pin sets high level and dir pin sets low level, mskdata pin puts out high level and wait for synchronized frame. (point a) (3) after a synchronized frame is detected, mskdata pin works as frame detect (fd) mode. fd goes to low level during the period of time ?t?, then fcln is sets to ?1? automatically. (point b, c) : waiting for the next synchronized flame. : having read 8bit data, mskdata pin puts out high level. fcln=0 mskdata ?low? y n rxsw=0 fsl=1 mskdata ?low? reading receive data fcln=0 have all receive data been read out? y : setting for fd signal put out from mskdata pin. : synchronized frame pattern detect or not ? : receive audio mute : 8 bit data received or not ? n n y fsl=0 fcln=1 (automatically) : setting flame detect (fd) enable : fd is disable automatically : setting for received flag (rdf) signal put out from mskdata pin.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 32 - (4) monitoring low level of mskdata pin, set rxsw=0 for audio signal mute. then set fsl=1 for received flag (rdf), signal put out from mskdata pin. (between c and d) (5) after 8 bit received data (md7?0) have been entered to the internal buffer from node rdata, mskdata pin goes to low level as rdf mode. (point d) (6) after cpu detects this low level at mskdata pin, please puts in 8 clock to sclk pin. then modulated data (rd7?0) put out from di/o pin synchronized with falling edge of sclk clock. (interval e) (7) after 8 clock have been put into sclk pin completely, mskdata pin goes to high level that shows all modulated data coming from di/o pin. (point f) (8) by repeating the steps (4), (5), (6), the data come out from di/o pin continuously. (9) after the necessary data have been read, dir pin sets to high level and fcln=0. then internal node rclk and rdata are set to ?1? for initializing and system waits for the next synchronization frame data. (interval g) this frame detection circuit does not have reset function. in case of stopping the sequence during the steps (1) to (8), please set again from the first step (1). especially, when mskdata pin goes out low level on frame detecting, fcln register is sets to ?1? automatically as written in (2). if you set fcln=0 during this operation, the date set ?0? is ignored. so please set the data again after mskdata pin puts out high level. 2.2) when frame detection is not used (1) when frame detection is not used, set msksw1 to 1 and msksw0 to 0 to start msk reception. (2) when the msk signal is received on the rxin pin, demodulated data is output successively on the mskdata pin via msk-bpf and msk-demodul ator in synchronization with the falling edge of the 1200hz or 2400hz clock signal output on the mskclk pin. (3) setting msksw1=1 and msksw0=1, reception mode comes to a stop. high level is output on the mskdata pin and msksw0 comes to high-z. at this time input high level or low level to mskdata pin.
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 33 - 18. recommended external application circuits 1) txa1 amplifier this is an operational amplifier required for typical transmit microphone. the gain should be less than 30db. to eliminate high frequency noise component over than 100khz from input signal, please compose 1 st or 2 nd order anti-aliasing filter. the following simplified schematic shows an example of 2 nd order anti-aliasing filter that has 30db gain and 10khz cut-off frequency. 2) txa2 amplifier this amplifier is used for adjusting the gain of the external tone signal. the gain should be less than 30db. to eliminate high frequency noise component over than 100khz from input signal, please compose 1 st or 2 nd order anti-aliasing filter. the following simplified schematic shows an example of 2 nd order anti-aliasing filter that has 30db gain and 10khz cut-off frequency. r3 c1=0.47uf r1=r2=10k _ + lsi c2 r1 txa1 txin txino 20 19 c3 c2=33pf c1 r2 r3=330k c3=2200pf r3 c1=0.47uf r1=r2=10k _ + lsi c2 r1 txa2 extin1 extino 17 16 c3 c2=33pf c1 r2 r3=330k c3=2200pf agnd extin2 c4 c4=0.047uf 21
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 34 - 3) rxa1 amplifier this is an operational amplifier suitable for receive gain adjuster and anti-aliasing filter to eliminate high frequency noise component over 100khz the gain should be less than 20db. the following simplified schematic shows an example of 2 nd order anti-aliasing filter that has 20db gain and 39khz cut-off frequency. 4) power supply stabilizing capacitors to connect capacitors between vdd and vss pin reduc e the ripple and noise included in power supply. these capacitors are mounted close to the device pins. 5) agnd, agndin pin stabilizing please decouple to vss level by the 0.3uf or larger capacitor. these capacitors are mounted close to the device pins. r3 c1=0.47uf r1=10 k _ + lsi c2 r1 rxa1 rxin rxino 11 10 c3 c2=33pf c1 r2 r2=9.1k r3=100k c3=560pf agnd lsi c2 dvdd vss1 c1 c2=10 f (electrolytic cap) c1=0.1 f (ceramic cap) vdd vss 7 8 9 avdd c1 c2 lsi c a gnd c=1 f (electrolytic capac itor) 15 c 14 a gndin
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 35 - 6) clock generation the clock source can be chosen from either built-in cr ystal oscillator circuit or externally supplied. when the built-in oscillator circuit is used, connect a 14.7456mhz crystal oscillator, a resistor, and capacitors as shown in fig. 1. AK2346A is designed to get a stable oscillation for the electrical equivalent circuitry of quartz crystal unit: resonance resistance 80 (max.) and shunt capacitance 1.5pf(max.). it is recommended that external 12pf capacitors should be connected so that the total load capacitance does not exceed the load capacitance 6pf (1.5pf+12pf//12pf) or less. these external components are mounted as close to the device pins as possible. when a clock signal is supplied externally, not only 3.6864mhz but also 7.3728mhz (twice higher than 3.6864mhz), 11.0592mhz (three times higher than 3.6864mhz), and 14.7456mhz (four times higher than 3.6864mhz) are supported. however, the internal frequency must always be set to 3.6864mhz by selecting division by 2, 3, or 4 for the divider in the subsequent stage. connect the clock signal as shown in fig. 2 or fig. 3 according to the clock amplitude level. the circuit in the first stage of the xin pin has a constant threshold voltage (0.8v). therefore, if the high level of the input clock is 1.5v or higher and the low level is 0.5v or lower, connect the clock signal as shown in fig. 2. if the input clock amplitude (p-p value) is between 0.2v and 1.0v, connect the clock signal as shown in fig. 3. when the clock is to be shared with peripheral ics, the clock must be input and output on the xin pin. the clock amplitude must not exceed the absolute maximum rating. lsi xin 12pf xout 1m 12pf 14.7456mhz fig. 1 lsi xin 3.6864mhz fig. 2 external clock in 6 5 7.3728mhz 11.0592mhz 14.7456mhz fig. 3 lsi xin 0.01uf xout 3.6864mhz extern al clock in 7.3728mhz 11.0592mhz 14.7456mhz
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 36 - 19. packaging ? marking [contents of xxxyz] y : date of manufacturing, last digit of the year ww : date of manufacturing, 2 digits of week number l : production lot number ? 24-pin qfnj mechanical outline (4.0 x 4.0 x 0.75mm, 0.5mm pitch) note: the exposed pad at the center of the back of the package must be connected to vss or opened. 2346a ywwl 2.40 2.40 0.400.1 c0.30 1 13 18 19 24 12 7 4.00.1 4.00.1 0.220.05 a 2.0 b 2.0 s part a 0.5 0.75max 0.70 0.05max 6 0.05 m s a 0.00-0.05 0.12-0.18 0.17-0.27 detailed chart in part a 0.05 s
asahi kasei [AK2346A] ms1289-e-02 2012/06 - 37 - 20. important notice important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no res ponsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containi ng it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distri butor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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